1. Field of the Invention
The present invention pertains to the field of integrated circuit devices. More particularly, this invention relates to a four transistor memory cell for memory circuits.
2. Background
A typical prior cache memory comprises an array of six transistor static random access memory (SRAM) cells. Each six transistor SRAM cell typically comprises a pair of cross coupled inverter circuits and a pair of pass gates. The cross coupled inverter circuits typically include pull-up transistors. The pull-up transistors prevent leakage currents in the SRAM cell from discharging of the data stored in the SRAM cell.
FIG. 1 illustrates a typical prior six transistor SRAM cell 10. The SRAM cell 10 comprises a set of six transistors Q1-Q6. The transistors Q1 and Q2 and the transistors Q3 and Q4 are arranged as cross coupled inverter circuits. The pass gate transistors Q5 and Q6 enable charge transfers between a pair of bit lines 14 and a pair of data storage nodes 15 and 16. The transistors Q5 and Q6 are activated via a word line 12.
The transistors Q1 is a pull-up transistor for the node 15, and the transistor Q3 is a pull-up transistor for the node 16. The pull-up transistors Q1 and Q3 prevent leakage currents in the SRAM cell 10 from discharging the node that stores the high level between accesses to the SRAM cell 10. As a consequence, the SRAM cell 10 does not require refreshing.
Unfortunately, the pull-up transistors Q1 and Q3 increase the integrated circuit die area required to implement the SRAM cell 10. Moreover, the aggregate of the pull-up transistors such as transistors Q1 and Q3 of each SRAM cell greatly increases the integrated circuit die area for such an SRAM.
In addition, such large SRAM cells severely limit the size of SRAM cache that can be implemented on chip with a processor. Moreover, such SRAM cells yield a decreased bit density for an SRAM implemented on a fixed area of an integrated circuit die.
Other prior SRAMs implement four transistor SRAM cells that do not employ pull-up transistors at the data storage nodes. Such prior four transistor SRAM memory cells employ extremely high resistive loads to accomplish the function of the pull-up transistors. Such high resistive loads are typically in the range of teraohms. Unfortunately, the manufacturing process for such SRAMs requires special masking layers. The special masking layers for the high resistive loads greatly increases the manufacturing cost of such SRAMs. In addition, such special masking layers are typically unsuitable for the process technology employed for manufacturing processor chips, thereby precluding the use of such SRAMs on chip with a processor.